40.6.9 Interrupt Enable Register
Name: | EMAC_IER |
Offset: | 0x28 |
Reset: | – |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
WOL | PTZ | PFR | HRESP | ROVR | |||||
Access | W | W | W | W | W | ||||
Reset | – | – | – | – | – |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TCOMP | TXERR | RLE | TUND | TXUBR | RXUBR | RCOMP | MFD | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit 14 – WOL Wake-On-LAN
Enable Wake-On-LAN interrupt.
Bit 13 – PTZ Pause Time Zero
Enable pause time zero interrupt.
Bit 12 – PFR Pause Frame Received
Enable pause frame received interrupt.
Bit 11 – HRESP Hresp Not OK
Enable Hresp not OK interrupt.
Bit 10 – ROVR Receive Overrun
Enable receive overrun interrupt.
Bit 7 – TCOMP Transmit Complete
Enable transmit complete interrupt.
Bit 6 – TXERR Transmit Error
Enable transmit buffers exhausted in mid-frame interrupt.
Bit 5 – RLE Retry Limit Exceeded
Enable retry limit exceeded interrupt.
Bit 4 – TUND Ethernet Transmit Buffer Underrun
Enable transmit underrun interrupt.
Bit 3 – TXUBR Transmit Used Bit Read
Enable transmit used bit read interrupt.
Bit 2 – RXUBR Receive Used Bit Read
Enable receive used bit read interrupt.
Bit 1 – RCOMP Receive Complete
Enable receive complete interrupt.
Bit 0 – MFD Management Frame Done
Enable management done interrupt.