40.6.7 Receive Status Register
This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing a one to them. It is not possible to set a bit to one by writing to the register.
| Name: | EMAC_RSR |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVR | REC | BNA | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – OVR Receive Overrun (cleared by writing a one to this bit)
The DMA block was unable to store the receive frame to memory, either because the bus was not granted in time or because a not OK hresp(bus error) was returned. The buffer is recovered if this happens.
Bit 1 – REC Frame Received (cleared by writing a one to this bit)
One or more frames have been received and placed in memory.
Bit 0 – BNA Buffer Not Available (cleared by writing a one to this bit)
An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared.