40.6.30 Receive Jabbers Register

EMAC_RJA is an EMAC statistics register. It resets to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

This receive statistics register is only incremented when the ‘Receive Enable’ bit is set in the Network Control Register (EMAC_NCR). To write to this register, bit 7 must be set in EMAC_NCR.

Name:	EMAC_RJA
Offset:	0x7C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	RJB[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – RJB[7:0] Receive Jabbers

An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in EMAC_NCFGR) in length and have either a CRC error, an alignment error or a receive symbol error.