40.6.12 PHY Maintenance Register
| Name: | EMAC_MAN |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SOF[1:0] | RW[1:0] | PHYA[4:1] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHYA[0] | REGA[4:0] | CODE[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DATA[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:30 – SOF[1:0] Start of Frame
Must be written to one for a valid frame.
Bits 29:28 – RW[1:0] PHY Read/Write Command
Any other value is an invalid PHY management frame.
| Value | Description |
|---|---|
| 1 | Write command |
| 2 | Read command |
Bits 27:23 – PHYA[4:0] PHY Address
Bits 22:18 – REGA[4:0] PHY Register Address
Specifies the register in the PHY to access.
Bits 17:16 – CODE[1:0] Must Be Two
Must be written to 2. Reads as written.
Bits 15:0 – DATA[15:0] PHY Transmit or Receive Data
For a write operation this is written with the data to be written to the PHY.
After a read operation this contains the data read from the PHY.