40.6.3 Network Status Register
| Name: | EMAC_NSR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IDLE | MDIO | ||||||||
| Access | R | R | |||||||
| Reset | 0 | x |
Bit 2 – IDLE PHY Management Logic Status
| Value | Description |
|---|---|
| 0 | The PHY logic is running. |
| 1 | The PHY management logic is idle (i.e., has completed). |
Bit 1 – MDIO MDIO Input Status
Returns status of the EMDIO pin. Use the PHY Maintenance Register to read managed frames rather than this bit.