40.6.4 Transmit Status Register
This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing a one to them. It is not possible to set a bit to one by writing to the register.
| Name: | EMAC_TSR |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UND | COMP | BEX | TGO | RLES | COL | UBR | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 6 – UND Transmit Underrun (cleared by writing a one to this bit)
Set when transmit DMA was not able to read data from memory, either because the bus was not granted in time, because a not OK hresp(bus error) was returned or because a used bit was read midway through frame transmission. If this occurs, the transmitter forces bad CRC.
Bit 5 – COMP Transmit Complete (cleared by writing a one to this bit)
Set when a frame has been transmitted.
Bit 4 – BEX Buffers Exhausted Mid-frame (cleared by writing a one to this bit)
If the buffers run out during transmission of a frame, then transmission stops, FCS shall be bad and tx_er asserted.
Bit 3 – TGO Transmit Go
If high transmit is active.
Bit 2 – RLES Retry Limit Exceeded (cleared by writing a one to this bit)
Bit 1 – COL Collision Occurred (cleared by writing a one to this bit)
Set by the assertion of collision.
Bit 0 – UBR Used Bit Read (cleared by writing a one to this bit)
Set when a transmit buffer descriptor is read with its used bit set.