40.6.45 User Input/Output Register
| Name: | EMAC_USRIO |
| Offset: | 0xC0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKEN | RMII | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – CLKEN Clock Enable
| Value | Description |
|---|---|
| 0 | Reduces power consumption when the treasurer is not used |
| 1 | Enables the transceiver input clock |
Bit 0 – RMII Reduced MII
When set, this bit enables the RMII operation mode. When reset, it selects the MII mode.