40.6.8 Interrupt Status Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
		WOL	PTZ	PFRE	HRESP	ROVR
Access		R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TCOMP	TXERR	RLEX	TUND	TXUBR	RXUBR	RCOMP	MFD
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 14 – WOL Wake-On-LAN (cleared on read)

Set when a WOL event has been triggered (This flag can be set even if the EMAC is not clocked).

Bit 13 – PTZ Pause Time Zero (cleared on read)

Set when the EMAC_PTR, 0x38 decrements to zero.

Bit 12 – PFRE Pause Frame Received (cleared on read)

Indicates a valid pause has been received.

Bit 11 – HRESP Hresp Not OK (cleared on read)

Set when the DMA block sees a bus error.

Bit 10 – ROVR Receive Overrun (cleared on read)

Set when the ‘Receive Overrun’ bit in EMAC_ISR gets set.

Bit 7 – TCOMP Transmit Complete (cleared on read)

Set when a frame has been transmitted.

Bit 6 – TXERR Transmit Error (cleared on read)

Transmit buffers exhausted in mid-frame - transmit error.

Bit 5 – RLEX Retry Limit Exceeded (cleared on read)

Bit 4 – TUND Ethernet Transmit Buffer Underrun (cleared on read)

The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK. Also set if a used bit is read mid-frame or when a new transmit queue pointer is written.

Bit 3 – TXUBR Transmit Used Bit Read (cleared on read)

Set when a transmit buffer descriptor is read with its used bit set.

Bit 2 – RXUBR Receive Used Bit Read (cleared on read)

Set when a receive buffer descriptor is read with its used bit set.

Bit 1 – RCOMP Receive Complete (cleared on read)

A frame has been stored in memory.

Bit 0 – MFD Management Frame Done (cleared on read)

The PHY Maintenance Register has completed its operation.

Name:	EMAC_ISR
Offset:	0x24
Reset:	0x00000000
Property:	Read/Write