40.6.11 Interrupt Mask Register
| Name: | EMAC_IMR |
| Offset: | 0x30 |
| Reset: | 0x00007FFF |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WOL | PTZ | PFR | HRESP | ROVR | |||||
| Access | R | R | R | R | R | ||||
| Reset | 1 | 1 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMP | TXERR | RLE | TUND | TXUBR | RXUBR | RCOMP | MFD | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 14 – WOL Wake-On-LAN
Wake-On-LAN interrupt masked.
Bit 13 – PTZ Pause Time Zero
Pause time zero interrupt masked.
Bit 12 – PFR Pause Frame Received
Pause frame received interrupt masked.
Bit 11 – HRESP Hresp Not OK
Hresp not OK interrupt masked.
Bit 10 – ROVR Receive Overrun
Receive overrun interrupt masked.
Bit 7 – TCOMP Transmit Complete
Transmit complete interrupt masked.
Bit 6 – TXERR Transmit Error
Transmit buffers exhausted in mid-frame interrupt masked.
Bit 5 – RLE Retry Limit Exceeded
Retry limit exceeded interrupt masked.
Bit 4 – TUND Ethernet Transmit Buffer Underrun
Transmit underrun interrupt masked.
Bit 3 – TXUBR Transmit Used Bit Read
Transmit used bit read interrupt masked.
Bit 2 – RXUBR Receive Used Bit Read
Receive used bit read interrupt masked.
Bit 1 – RCOMP Receive Complete
Receive complete interrupt masked.
Bit 0 – MFD Management Frame Done
Management done interrupt masked.