40.6.10 Interrupt Disable Register

Name: EMAC_IDR
Offset: 0x2C
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  WOLPTZPFRHRESPROVR   
Access WWWWW 
Reset  
Bit 76543210 
 TCOMPTXERRRLETUNDTXUBRRXUBRRCOMPMFD 
Access WWWWWWWW 
Reset  

Bit 14 – WOL Wake-On-LAN

Disable Wake-On-LAN interrupt.

Bit 13 – PTZ Pause Time Zero

Disable pause time zero interrupt.

Bit 12 – PFR Pause Frame Received

Disable pause frame received interrupt.

Bit 11 – HRESP Hresp Not OK

Disable Hresp not OK interrupt.

Bit 10 – ROVR Receive Overrun

Disable receive overrun interrupt.

Bit 7 – TCOMP Transmit Complete

Disable transmit complete interrupt.

Bit 6 – TXERR Transmit Error

Disable transmit buffers exhausted in mid-frame interrupt.

Bit 5 – RLE Retry Limit Exceeded

Disable retry limit exceeded interrupt.

Bit 4 – TUND Ethernet Transmit Buffer Underrun

Disable transmit underrun interrupt.

Bit 3 – TXUBR Transmit Used Bit Read

Disable transmit used bit read interrupt.

Bit 2 – RXUBR Receive Used Bit Read

Disable receive used bit read interrupt.

Bit 1 – RCOMP Receive Complete

Disable receive complete interrupt.

Bit 0 – MFD Management Frame Done

Disable management done interrupt.