50.9.10 CAN Transfer Command Register
This register initializes several transfer requests at the same time.
| Name: | CAN_TCR |
| Offset: | 0x0024 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TIMRST | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MB15 | MB14 | MB13 | MB12 | MB11 | MB10 | MB9 | MB8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MB7 | MB6 | MB5 | MB4 | MB3 | MB2 | MB1 | MB0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bit 31 – TIMRST Timer Reset
Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – MBx Transfer Request for Mailbox x
This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx.
When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., MB0 will be transferred before MB1).
| Mailbox Object Type | Description |
| Receive | Receives the next message |
| Receive with Overwrite | Triggers a new reception |
| Transmit | Sends data prepared in the mailbox as soon as possible |
| Consumer | Sends a remote frame |
| Producer | Sends data prepared in the mailbox after receiving a remote frame from a consumer |