50.9.9 CAN Error Counter Register
| Name: | CAN_ECR |
| Offset: | 0x0020 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TEC[8] | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TEC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 24:16 – TEC[8:0] Transmit Error Counter
When a transmitter sends an Error flag, TEC is increased by 8, except when:
– the transmitter is error passive and detects an acknowledgment error because of not detecting a dominant ACK and does not detect a dominant bit while sending its Passive Error flag,
– the transmitter sends an error because a stuff error occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant.
When a transmitter detects a bit error while sending an Active Error or Overload flag, the TEC will be increased by 8.
Any node tolerates up to 7 consecutive dominant bits after sending an Active Error, Passive Error or Overload flag. After detecting the 14th consecutive dominant bit (in case of an Active Error or Overload flag) or after detecting the 8th consecutive dominant bit following a Passive Error flag, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8.
After a successful transmission the TEC is decreased by 1 unless it was already 0.
Bits 7:0 – REC[7:0] Receive Error Counter
When a receiver detects an error, REC will be increased by one, except when the detected error is a bit error while sending an Active Error or Overload flag.
When a receiver detects a dominant bit as the first bit after sending an Error flag, REC is increased by 8.
When a receiver detects a bit error while sending an Active Error flag, REC is increased by 8.
Any node tolerates up to 7 consecutive dominant bits after sending an Active Error, Passive Error or Overload flag. After detecting the 14th consecutive dominant bit (in case of an Active Error or Overload flag) or after detecting the 8th consecutive dominant bit following a Passive Error flag, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8.
After successful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127.