50.9.1 CAN Mode Register
This register can only be written if the WPEN bit is cleared in the CAN Write Protection Mode Register.
| Name: | CAN_MR |
| Offset: | 0x0000 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXSYNC[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DRPT | TIMFRZ | TTM | TEOF | OVL | ABM | LPM | CANEN | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 26:24 – RXSYNC[2:0] Reception Synchronization Stage (not readable)
This field allows configuration of the reception stage of the macrocell (for debug purposes only)
| Value | Name | Description |
|---|---|---|
| 0 | DOUBLE_PP | Rx Signal with Double Synchro Stages (2 Positive Edges) |
| 1 | DOUBLE_PN | Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) |
| 2 | SINGLE_P | Rx Signal with Single Synchro Stage (Positive Edge) |
| 3 | NONE | Rx Signal with No Synchro Stage |
Bit 7 – DRPT Disable Repeat
| Value | Description |
|---|---|
| 0 | When a transmit mailbox loses the bus arbitration, the transfer request remains pending. |
| 1 | When a transmit mailbox loses the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx. |
Bit 6 – TIMFRZ Enable Timer Freeze
| Value | Description |
|---|---|
| 0 | The internal timer continues to be incremented after it reached 0xFFFF. |
| 1 | The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See Freezing the Internal Timer Counter. |
Bit 5 – TTM Disable/Enable Time-triggered Mode
| Value | Description |
|---|---|
| 0 | Time-triggered mode is disabled. |
| 1 | Time-triggered mode is enabled. |
Bit 4 – TEOF Timestamp messages at each end of Frame
| Value | Description |
|---|---|
| 0 | The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame. |
| 1 | The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame. |
Bit 3 – OVL Disable/Enable Overload Frame
| Value | Description |
|---|---|
| 0 | No overload frame is generated. |
| 1 | An overload frame is generated after each successful reception for mailboxes configured in Receive with/without Overwrite mode, Producer and Consumer. |
Bit 2 – ABM Disable/Enable Autobaud/Listen mode
| Value | Description |
|---|---|
| 0 | Disable Autobaud/Listen mode. |
| 1 | Enable Autobaud/Listen mode. |
Bit 1 – LPM Disable/Enable Low-power Mode
The CAN controller enters Low-power mode once all pending messages have been transmitted.
| Value | Description |
|---|---|
| 0 | Disable Low-power mode. |
| 1 | Enable Low-power mode. |
Bit 0 – CANEN CAN Controller Enable
| Value | Description |
|---|---|
| 0 | The CAN controller is disabled. |
| 1 | The CAN controller is enabled. |