50.9.5 CAN Status Register
| Name: | CAN_SR |
| Offset: | 0x0010 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OVLSY | TBSY | RBSY | BERR | FERR | AERR | SERR | CERR | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TSTP | TOVF | WAKEUP | SLEEP | BOFF | ERRP | WARN | ERRA | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MB15 | MB14 | MB13 | MB12 | MB11 | MB10 | MB9 | MB8 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MB7 | MB6 | MB5 | MB4 | MB3 | MB2 | MB1 | MB0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – OVLSY Overload busy
It is automatically reset when the bus is not transmitting an overload frame.
| Value | Description |
|---|---|
| 0 | The CAN transmitter is not transmitting an overload frame. |
| 1 | The CAN transmitter is transmitting an overload frame. |
Bit 30 – TBSY Transmitter Busy
Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting.
| Value | Description |
|---|---|
| 0 | Th CAN transmitter is not transmitting a frame. |
| 1 | The CAN transmitter is transmitting a frame. |
Bit 29 – RBSY Receiver Busy
Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving.
| Value | Description |
|---|---|
| 0 | The CAN receiver is not receiving a frame. |
| 1 | The CAN receiver is receiving a frame. |
Bit 28 – BERR Bit Error (automatically cleared by reading CAN_SR)
A bit error is set when the bit value monitored on the line is different from the bit value sent.
| Value | Description |
|---|---|
| 0 | No bit error occurred during a previous transfer. |
| 1 | A bit error occurred during a previous transfer. |
Bit 27 – FERR Form Error (automatically cleared by reading CAN_SR)
A form error results from violations on one or more of the fixed form of the following bit fields:
| Value | Description |
|---|---|
| 0 | No form error occurred during a previous transfer |
| 1 | A form error occurred during a previous transfer – CRC delimiter – ACK delimiter – End of frame – Error delimiter – Overload delimiter |
Bit 26 – AERR Acknowledgment Error (automatically cleared by reading CAN_SR)
An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs.
| Value | Description |
|---|---|
| 0 | No acknowledgment error occurred during a previous transfer. |
| 1 | An acknowledgment error occurred during a previous transfer. |
Bit 25 – SERR Mailbox Stuffing Error (automatically cleared by reading CAN_SR)
A form error results from the detection of more than five consecutive bit with the same polarity.
| Value | Description |
|---|---|
| 0 | No stuffing error occurred during a previous transfer. |
| 1 | A stuffing error occurred during a previous transfer. |
Bit 24 – CERR Mailbox CRC Error (automatically cleared by reading CAN_SR)
A CRC error has been detected during last reception.
| Value | Description |
|---|---|
| 0 | No CRC error occurred during a previous transfer. |
| 1 | A CRC error occurred during a previous transfer. |
Bit 23 – TSTP Timestamp (automatically cleared by reading CAN_SR)
| Value | Description |
|---|---|
| 0 | No bus activity has been detected. |
| 1 | A start of frame or an end of frame has been detected (according to the CAN_MR.TEOF field). |
Bit 22 – TOVF Timer Overflow (automatically cleared by reading CAN_SR)
| Value | Description |
|---|---|
| 0 | The timer has not rolled over FFFFh to 0000h. |
| 1 | The timer rolls over FFFFh to 0000h. |
Bit 21 – WAKEUP CAN Controller is not in Low-power Mode
When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN controller enters Low-power mode.
| Value | Description |
|---|---|
| 0 | The CAN controller is in Low-power mode. |
| 1 | The CAN controller is not in Low-power mode. |
Bit 20 – SLEEP CAN Controller in Low-power Mode
This flag is automatically reset when Low-power mode is disabled
| Value | Description |
|---|---|
| 0 | The CAN controller is not in Low-power mode. |
| 1 | The CAN controller is in Low-power mode. |
Bit 19 – BOFF Bus Off Mode (automatically cleared by reading CAN_SR)
This flag is set depending on the TEC counter value. A node is in Bus Off state when the TEC counter is greater or equal to 256 (decimal).
| Value | Description |
|---|---|
| 0 | The CAN controller has not reached Bus Off mode. |
| 1 | The CAN controller has reached Bus Off mode since the last read of CAN_SR. |
| 0 | The CAN controller is not in Bus Off mode. |
| 1 | The CAN controller is in Bus Off mode. |
Bit 18 – ERRP Error Passive Mode (automatically cleared by reading CAN_SR)
This flag is set depending on TEC and REC counters values.
A node is in Error Passive state when the TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal).
| Value | Description |
|---|---|
| 0 | The CAN controller has not reached Error Passive mode since the last read of CAN_SR. |
| 1 | The CAN controller has reached Error Passive mode since the last read of CAN_SR. |
| 0 | The CAN controller is not in Error Passive mode. |
| 1 | The CAN controller is in Error Passive mode. |
Bit 17 – WARN Warning Limit (automatically cleared by reading CAN_SR)
This flag is set depending on TEC and REC counter values. It is set when at least one of the counter values has reached a value greater or equal to 96.
| Value | Description |
|---|---|
| 0 | The CAN controller Warning Limit has not been reached since the last read of CAN_SR. |
| 1 | The CAN controller Warning Limit has been reached since the last read of CAN_SR. |
| 0 | The CAN controller Warning Limit is not reached. |
| 1 | The CAN controller Warning Limit is reached. |
Bit 16 – ERRA Error Active Mode (automatically cleared by reading CAN_SR)
This flag is set depending on TEC and REC counter values. It is set when a node is neither in Error Passive mode nor in Bus Off mode.
| Value | Description |
|---|---|
| 0 | The CAN controller has not reached Error Active mode since the last read of CAN_SR. |
| 1 | The CAN controller has reached Error Active mode since the last read of CAN_SR. |
| 0 | The CAN controller is not in Error Active mode. |
| 1 | The CAN controller is in Error Active mode. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – MBx Mailbox x Event
An event corresponds to the MRDY or MABT bit in CAN_MSRx.
| Value | Description |
|---|---|
| 0 | No event occurred on Mailbox x. |
| 1 | An event occurred on Mailbox x. |