50.9.6 CAN Baudrate Register
This register can only be written if the WPEN bit is cleared in the CAN Write Protection Mode Register.
Any modification on one of the CAN_BR fields must be done while the CAN module is disabled.
To compute the different bit timings, see CAN Bit Timing Configuration.
Name: | CAN_BR |
Offset: | 0x0014 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
SMP | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
BRP[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
SJW[1:0] | PROPAG[2:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PHASE1[2:0] | PHASE2[2:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 24 – SMP Sampling Mode
0 (ONCE): The incoming bit stream is sampled once at sample point.
1 (THREE): The incoming bit stream is sampled three times with a period of a peripheral clock, centered on sample point.
SMP Sampling mode is automatically disabled if BRP = 0.
Bits 22:16 – BRP[6:0] Baudrate Prescaler
This field allows user to program the period of the CAN system clock to determine the individual bit timing.
The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
Bits 13:12 – SJW[1:0] Re-synchronization Jump Width
To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization.
Bits 10:8 – PROPAG[2:0] Programming Time Segment
This part of the bit time is used to compensate for the physical delay times within the network.
Bits 6:4 – PHASE1[2:0] Phase 1 Segment
This phase is used to compensate for edge phase error.
Bits 2:0 – PHASE2[2:0] Phase 2 Segment
This phase is used to compensate the edge phase error.