50.9.4 CAN Interrupt Mask Register
| Name: | CAN_IMR |
| Offset: | 0x000C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BERR | FERR | AERR | SERR | CERR | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TSTP | TOVF | WAKEUP | SLEEP | BOFF | ERRP | WARN | ERRA | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MB15 | MB14 | MB13 | MB12 | MB11 | MB10 | MB9 | MB8 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MB7 | MB6 | MB5 | MB4 | MB3 | MB2 | MB1 | MB0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 28 – BERR Bit Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | Bit Error interrupt is disabled. |
| 1 | Bit Error interrupt is enabled. |
Bit 27 – FERR Form Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | Form Error interrupt is disabled. |
| 1 | Form Error interrupt is enabled. |
Bit 26 – AERR Acknowledgment Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | Acknowledgment Error interrupt is disabled. |
| 1 | Acknowledgment Error interrupt is enabled. |
Bit 25 – SERR Stuffing Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | Bit Stuffing Error interrupt is disabled. |
| 1 | Bit Stuffing Error interrupt is enabled. |
Bit 24 – CERR CRC Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | CRC Error interrupt is disabled. |
| 1 | CRC Error interrupt is enabled. |
Bit 23 – TSTP Timestamp Interrupt Mask
| Value | Description |
|---|---|
| 0 | TSTP interrupt is disabled. |
| 1 | TSTP interrupt is enabled. |
Bit 22 – TOVF Timer Overflow Interrupt Mask
| Value | Description |
|---|---|
| 0 | TOVF interrupt is disabled. |
| 1 | TOVF interrupt is enabled. |
Bit 21 – WAKEUP Wakeup Interrupt Mask
| Value | Description |
|---|---|
| 0 | WAKEUP interrupt is disabled. |
| 1 | WAKEUP interrupt is enabled. |
Bit 20 – SLEEP Sleep Interrupt Mask
| Value | Description |
|---|---|
| 0 | SLEEP interrupt is disabled. |
| 1 | SLEEP interrupt is enabled. |
Bit 19 – BOFF Bus Off Mode Interrupt Mask
| Value | Description |
|---|---|
| 0 | BOFF interrupt is disabled. |
| 1 | BOFF interrupt is enabled. |
Bit 18 – ERRP Error Passive Mode Interrupt Mask
| Value | Description |
|---|---|
| 0 | ERRP interrupt is disabled. |
| 1 | ERRP interrupt is enabled. |
Bit 17 – WARN Warning Limit Interrupt Mask
| Value | Description |
|---|---|
| 0 | Warning Limit interrupt is disabled. |
| 1 | Warning Limit interrupt is enabled. |
Bit 16 – ERRA Error Active Mode Interrupt Mask
| Value | Description |
|---|---|
| 0 | ERRA interrupt is disabled. |
| 1 | ERRA interrupt is enabled. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – MBx Mailbox x Interrupt Mask
| Value | Description |
|---|---|
| 0 | Mailbox x interrupt is disabled. |
| 1 | Mailbox x interrupt is enabled. |