50.9.16 CAN Message ID Register

This register can only be written if the WPEN bit is cleared in the CAN Write Protection Mode Register.

To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers.

Name:	CAN_MIDx
Offset:	0x0208 + x*0x20 [x=0..7]
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
			MIDE	MIDvA[10:6]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	MIDvA[5:0]						MIDvB[17:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MIDvB[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MIDvB[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 29 – MIDE Identifier Version

This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version 2.0 Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages.

Bits 28:18 – MIDvA[10:0] Identifier for Standard Frame mode

Bits 17:0 – MIDvB[17:0] Complementary bits for identifier in Extended Frame mode

If MIDE is cleared, MIDvB value is 0.