50.9.2 CAN Interrupt Enable Register

Name: CAN_IER
Offset: 0x0004
Reset: 
Property: Write-only

Bit 3130292827262524 
    BERRFERRAERRSERRCERR 
Access WWWWW 
Reset  
Bit 2322212019181716 
 TSTPTOVFWAKEUPSLEEPBOFFERRPWARNERRA 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 MB15MB14MB13MB12MB11MB10MB9MB8 
Access WWWWWWWW 
Reset  
Bit 76543210 
 MB7MB6MB5MB4MB3MB2MB1MB0 
Access WWWWWWWW 
Reset  

Bit 28 – BERR Bit Error Interrupt Enable

ValueDescription
0

No effect.

1

Enable Bit Error interrupt.

Bit 27 – FERR Form Error Interrupt Enable

ValueDescription
0

No effect.

1

Enable Form Error interrupt.

Bit 26 – AERR Acknowledgment Error Interrupt Enable

ValueDescription
0

No effect.

1

Enable Acknowledgment Error interrupt.

Bit 25 – SERR Stuffing Error Interrupt Enable

ValueDescription
0

No effect.

1

Enable Stuffing Error interrupt.

Bit 24 – CERR CRC Error Interrupt Enable

ValueDescription
0

No effect.

1

Enable CRC Error interrupt.

Bit 23 – TSTP TimeStamp Interrupt Enable

ValueDescription
0

No effect.

1

Enable TSTP interrupt.

Bit 22 – TOVF Timer Overflow Interrupt Enable

ValueDescription
0

No effect.

1

Enable TOVF interrupt.

Bit 21 – WAKEUP Wakeup Interrupt Enable

ValueDescription
0

No effect.

1

Enable SLEEP interrupt.

Bit 20 – SLEEP Sleep Interrupt Enable

ValueDescription
0

No effect.

1

Enable SLEEP interrupt.

Bit 19 – BOFF Bus Off Mode Interrupt Enable

ValueDescription
0

No effect.

1

Enable BOFF interrupt.

Bit 18 – ERRP Error Passive Mode Interrupt Enable

ValueDescription
0

No effect.

1

Enable ERRP interrupt.

Bit 17 – WARN Warning Limit Interrupt Enable

ValueDescription
0

No effect.

1

Enable WARN interrupt.

Bit 16 – ERRA Error Active Mode Interrupt Enable

ValueDescription
0

No effect.

1

Enable ERRA interrupt.

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – MBx Mailbox x Interrupt Enable

ValueDescription
0

No effect.

1

Enable Mailbox x interrupt.