29.6.8 Status

Important: For PIC32CM LS00/LS60 Non-Secure accesses, write accesses (W*) are allowed only if Non-Secure Write is set in NONSEC register.
Name: STATUS
Offset: 0x18
Reset: 0x00xx (x determined from latest Set DAL or Chip Erase command)
Property: Write-Secure

Bit 15141312111098 
 Reserved        
Access R/R/R 
Reset 0 
Bit 76543210 
    DALFUSE[1:0]READYLOADPRM 
Access R/R/RR/R/RR/R/RR/R/RR/R/R 
Reset xx000 

Bit 15 – Reserved

Bits 4:3 – DALFUSE[1:0] DAL Fuse Value

This field is the current Debug Access Level fuse value.
CAUTION: This bit field does not reflect the current Debug Access Level (DAL) if DALUN bit == 1 (NVMCTRL.SECCTRL) but the Debug Access Level which will be applied once DALUN == 0.
ValueNameDescription
0DAL0DAL = 0 : Access to very limited features.
1DAL1DAL = 1 (PIC32CM LS00/LS60 only): Access to all non-secure memory. Can debug non-secure CPU code.
2DAL2DAL = 2 : Access to all memory. Can debug Secure and non-secure CPU code.
3-Reserved

Bit 2 – READY NVM Ready

ValueDescription
0The NVM controller is busy programming or erasing.
1The NVM controller is ready to accept a new command.

Bit 1 – LOAD NVM Page Buffer Active Loading

This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBC) command is given.

Bit 0 – PRM Power Reduction Mode

This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly.

PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly.

ValueDescription
0NVM is not in power reduction mode.
1NVM is in power reduction mode.