4.14.3.8 SFR I/O Calibration 1 Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.

Name: SFR_CAL1
Offset: 0xB4
Reset: 0x00000084
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
        TEST_M 
Access R/W 
Reset 0 
Bit 76543210 
 CALP_M[3:0]CALN_M[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 10000100 

Bit 8 – TEST_M Enable Calibration of Low/High Level Output Impedance of Pads with VDDIOM Supply

Enables calibration bits to adjust the low/high level output impedance of pads with power supply input VDDIOM.

Bits 7:4 – CALP_M[3:0] Calibration of High Level Output Impedance of Pads with VDDIOM Supply

Adjusts the high level output impedance of pads with power supply input VDDIOM.

ValueName
0000 Minimum output impedance value
1111 Maximum output impedance value

Bits 3:0 – CALN_M[3:0] Calibration of Low Level Output Impedance of Pads with VDDIOM Supply

Adjusts the low level output impedance of pads with power supply input VDDIOM.

ValueName
0000 Maximum output impedance value
1111 Minimum output impedance value