4.14.3.12 PUF Restrict User Context 0 Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.

CAUTION: SFR_PUFRUCRx and SFR_PUFWORUCRx registers are connected to the same input by an OR gate.

Name:	SFR_PUFRUCR0
Offset:	0x20C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	RESTRICT_USER_CONTEXT_0[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RESTRICT_USER_CONTEXT_0[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RESTRICT_USER_CONTEXT_0[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RESTRICT_USER_CONTEXT_0[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – RESTRICT_USER_CONTEXT_0[31:0] Value Connected to qk_restrict_user_context_0 input for QK

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.