4.14.3.3 OHCI Interrupt Status Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.
| Name: | SFR_OHCIISR |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RIS2 | RIS1 | RIS0 | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bits 0, 1, 2 – RISx OHCI Resume Interrupt Status Port x
| Value | Description |
|---|---|
| 0 | OHCI port resume is not detected. |
| 1 | OHCI port resume is detected. |