4.14.3.1 EBI Chip Select Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.

Name: SFR_CCFG_EBICSA
Offset: 0x04
Reset: 0x00000300
Property: Read/Write

Bit 3130292827262524 
       DDR_MP_ENNFD0_ON_D16 
Access R/WR/W 
Reset 00 
Bit 2322212019181716 
    DQIEN_F     
Access R/W 
Reset 0 
Bit 15141312111098 
       EBI_DBPDCEBI_DBPUC 
Access R/WR/W 
Reset 11 
Bit 76543210 
      EBI_CS2AEBI_CS1A  
Access R/WR/W 
Reset 00 

Bit 25 – DDR_MP_EN DDR Multiport Enable

ValueDescription
0 DDR Multiport is disabled (default).
1 DDR Multiport is enabled, performance is increased.

Bit 24 – NFD0_ON_D16 NAND Flash Databus Selection

ValueDescription
0 NAND Flash I/Os are connected to D0–D7 (default).
1 NAND Flash I/Os are connected to D16–D23.

Bit 20 – DQIEN_F Force Analog Input Comparator Configuration

ValueDescription
0 No effect
1 Enables the input comparator in the VDDIOM I/O data lines. Must be set to one in an initialization phase whenever an MPDDRC external component (DDR2 or LPDDR) and an SMC external component (e.g., NAND Flash) are multiplexed on the D0-D15 bus.

Bit 9 – EBI_DBPDC EBI Data Bus Pulldown Configuration

ValueDescription
0 EBI D0–D15 Data Bus bits are not internally pulled down.
1 EBI D0–D15 Data Bus bits are internally pulled down to the ground.

Bit 8 – EBI_DBPUC EBI Data Bus Pullup Configuration

ValueDescription
0 EBI D0–D15 Data Bus bits are internally pulled up to the VDDIOM power supply.
1 EBI D0–D15 Data Bus bits are not internally pulled up.

Bit 2 – EBI_CS2A EBI Chip Select 2 Assignment

ValueDescription
0 EBI Chip Select 2 is only assigned to the SMC and EBI_NCS2 behaves as defined by the SMC.
1 EBI Chip Select 2 is assigned to the SMC and the NAND Flash Logic is activated.

Bit 1 – EBI_CS1A EBI Chip Select 1 Assignment

ValueDescription
0 EBI Chip Select 1 is assigned to the Static Memory Controller (SMC).
1 EBI Chip Select 1 is assigned to the AHB Multiport DDR-SDRAM Controller (MPDDRC).