4.14.3.18 TSU Configuration Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.
| Name: | SFR_TSU_CFG |
| Offset: | 0x250 |
| Reset: | 0x00000043 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WIDTH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | |
Bits 7:0 – WIDTH[7:0] Number of TSU Cycles to Increase GTSUCOMP Width
GTSUCOMP_cycles = WIDTH +1