4.14.3.5 UTMI Full-Speed Trimming Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.

Name: SFR_UTMIFSTRIM
Offset: 0x38
Reset: 0x00430211
Property: Read/Write

Bit 3130292827262524 
  ZP_CAL[2:0] ZN_CAL[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
  ZP[2:0] ZN[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 100011 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
          
Access  
Reset  

Bits 30:28 – ZP_CAL[2:0] FS Transceiver PMOS Impedance Calibration

Adjusts the FS transceiver PMOS output impedance calibration.

ValueName
0 Default
1
2
3 Higher
4 Lower
5
6
7

Bits 26:24 – ZN_CAL[2:0] FS Transceiver NMOS Impedance Calibration

Adjusts the FS transceiver NMOS output impedance calibration.

ValueName
0 Default
1
2
3 Higher
4 Lower
5
6
7

Bits 22:20 – ZP[2:0] FS Transceiver PMOS Impedance Trimming

Adjusts the FS transceiver PMOS output impedance.

ValueName
0 Lower
1
2
3
4 Default
5
6
7 Higher

Bits 18:16 – ZN[2:0] FS Transceiver NMOS Impedance Trimming

Adjusts the FS transceiver NMOS output impedance.

ValueName
0 Higher
1
2
3
4 Default
5
6
7 Lower