4.14.3.2 OHCI Interrupt Configuration Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.
| Name: | SFR_OHCIICR |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| UDPPUDIS | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SUSP2 | SUSP1 | SUSP0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| APPSTART | ARIE | RES2 | RES1 | RES0 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 23 – UDPPUDIS Reserved
| Value | Description |
|---|---|
| 0 | Must write 0. |
Bits 8, 9, 10 – SUSPx USB PORTx
| Value | Description |
|---|---|
| 0 | Does not suspend USB PORTx. |
| 1 | Forces PORTx suspend. |
Bit 5 – APPSTART Reserved
| Value | Description |
|---|---|
| 0 | Must write 0. |
Bit 4 – ARIE OHCI Asynchronous Resume Interrupt Enable
| Value | Description |
|---|---|
| 0 | Disables interrupt. |
| 1 | Enables interrupt. |
Bits 0, 1, 2 – RESx USB PORTx Reset
| Value | Description |
|---|---|
| 0 | No effect (USB PORTx reset released, default value) |
| 1 | Resets USB PORTx. |