4.14.3.16 FLEXRAMS Clock Gating Disable Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.
| Name: | SFR_FLEXRAMS_CLKG_DIS |
| Offset: | 0x220 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLEX1_CLKG_DIS | FLEX0_CLKG_DIS | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – FLEX1_CLKG_DIS Clock Gating Disable for FLEXRAM1
| Value | Description |
|---|---|
| 0 | Clock Gating is enabled. |
| 1 | Clock Gating is disabled. |
Bit 0 – FLEX0_CLKG_DIS Clock Gating Disable for FLEXRAM0
| Value | Description |
|---|---|
| 0 | Clock Gating is enabled. |
| 1 | Clock Gating is disabled. |