4.14.3.10 PUFSRAM Domain Control Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.

Name: SFR_PUFCTL
Offset: 0x200
Reset: 0x00000148
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
       PHGPLG 
Access RR 
Reset 01 
Bit 76543210 
  ALWAYSONEPUFLTMPUFDISPUFRSTPONOFFLZPONOFFHZPONOFFM 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 1001000 

Bit 9 – PHG PUFSRAM Power High Status

CAUTION: PHG is only 1 when the two power switches (HiZ and LoZ) are on. In other case PHG=0 and PLG=1.

ValueDescription
0 PUFSRAM domain is not powered.
1 PUFSRAM domain is powered.

Bit 8 – PLG PUFSRAM Power Low Status

ValueDescription
0 PUFSRAM domain is powered.
1 PUFSRAM domain is not powered.

Bit 6 – ALWAYSONE Must always be programmed to 1

Bit 5 – PUFLTM PUF Lab Test Mode

ValueDescription
0 No effect
1 Enters Test mode when PUFRST=0.

Bit 4 – PUFDIS Disable the PUF

CAUTION: This bit is write-once until the next chip reset.

ValueDescription
0 No effect
1 PUF clock and psel signals are disabled by HW and PUFSRAM domain is off.

Bit 3 – PUFRST Reset for PUF IP

ValueDescription
0 PUF is active.
1 PUF is in Reset mode.

Bit 2 – PONOFFLZ Controls Power Switch Low Z if PONOFFM=1

ValueDescription
0 Power switch Low Z is off.
1 Power switch Low Z is on.

Bit 1 – PONOFFHZ Controls Power Switch High Z if PONOFFM=1

ValueDescription
0 Power switch High Z is off.
1 Power switch High Z is on.

Bit 0 – PONOFFM PUFSRAM Power Switches Controlled Manually

CAUTION: When controlling power switches manually, apply the following sequence:
  1. Write PONOFFHZ to 1.
  2. Wait the time defined in the fuses (from 20 μs to 80 μs).
  3. Write PONOFFLZ to 1.
ValueDescription
0 Power switches are automatically controlled by SYSC at startup.
1 Power switches are manually controlled by the PONOFFLZ and PONOFFHZ bits.