4.14.3.7 SFR Light Sleep Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register.
The following configuration values are valid for all listed LSx bit names of this register:
0: Disables Light Sleep mode.
1: Enables Light Sleep mode.
| Name: | SFR_LS |
| Offset: | 0xA0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MEM_POWER_GATING_ULP1_EN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LS13 | LS12 | LS11 | LS10 | LS9 | LS8 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LS7 | LS6 | LS5 | LS4 | LS3 | LS2 | LS1 | LS0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 16 – MEM_POWER_GATING_ULP1_EN Light Sleep Value for ULP1 Power-Gated Memories
The memory power gating can be automatically enabled when entering ULP1 Low-power mode. Refer to the section “Electrical Characteristics”.
| Value | Description |
|---|---|
| 0 | Light Sleep mode is not activated by the MEM_POWER_GATING_ULP1 output signal from the PMC. |
| 1 | Light Sleep mode is activated when the MEM_POWER_GATING_ULP1 output signal from the PMC is activated. |