42.8.10 Synchronization Busy
| Name: | SYNCBUSY |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CTRLD | ENABLE | SWRST | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – CTRLD Control D
This bit is cleared when the synchronization of Control D register between the clock domains is complete.
This bit is set when the synchronization of Control D register between the clock domains is started.
Bit 1 – ENABLE Enable
This bit is cleared when the synchronization of Enable bit between the clock domains is complete.
This bit is set when the synchronization of Enable bit between the clock domains is started.
Bit 0 – SWRST Software Reset
This bit is cleared when the synchronization of Software Reset bit between the clock domains is complete.
This bit is set when the synchronization of Software Reset bit between the clock domains is started.