42.8.8 Interrupt Flag


Bit	7	6	5	4	3	2	1	0
			PRST	VLCDST	VLCDRT	FC2O	FC1O	FC0O
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0

Bit 5 – PRST Pump Run Status Toggle

The status of the pump inside the LCD power macro is changed. Either pump start to run or stop.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Pump Run Status Toggle flag.

Bit 4 – VLCDST VLCD Status Toggle

The status of VLCD is changed, which indicates that the relation of target VLCD and VDD33 has changed.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the VLCD Status Toggle flag.

Bit 3 – VLCDRT VLCD Ready Toggle

The status of the VLCD Ready is changed.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the VLCD Ready Toggle flag.

Bit 2 – FC2O Frame Counter 2 Overflow

This flag is set when the frame counter 2 overflows and will generate an interrupt request if the Frame Counter 2 Overflow Enable bit in Interrupt Enable Set register (INTENSET.FC2O) is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Frame Counter 2 Overflow interrupt flag.

Bit 1 – FC1O Frame Counter 1 Overflow

This flag is set when the frame counter 1 overflows and will generate an interrupt request if the Frame Counter 1 Overflow Enable bit in Interrupt Enable Set register (INTENSET.FC1O) is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Frame Counter 1 Overflow interrupt flag.

Bit 0 – FC0O Frame Counter 0 Overflow

This flag is set when the frame counter 0 overflows, and will generate an interrupt request if the Frame Counter 0 Overflow Enable bit in Interrupt Enable Set register (INTENSET.FC0O) is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Frame Counter 0 Overflow interrupt flag.

Name:	INTFLAG
Offset:	0x0F
Reset:	0x00
Property:	-