42.8.1 Control A


Bit	31	30	29	28	27	26	25	24
						RRF[2:0]
Access						RW	RW	RW
Reset						0	0	0


Bit	23	22	21	20	19	18	17	16
	DMFCS[1:0]		PRF[1:0]		XVLCD		BIAS[1:0]
Access	RW	RW	RW	RW	RW		RW	RW
Reset	0	0	0	0	0		0	0


Bit	15	14	13	12	11	10	9	8
		CKDIV[2:0]					PRESC[1:0]
Access		RW	RW	RW			RW	RW
Reset		0	0	0			0	0


Bit	7	6	5	4	3	2	1	0
		RUNSTDBY	WMOD	DUTY[2:0]			ENABLE	SWRST
Access		RW	RW	RW	RW	RW	RW	RW
Reset		0	0	0	0	0	0	0

Bits 26:24 – RRF[2:0] Reference Refresh Frequency

These bits define the bias reference refresh frequency

These bits are not synchronized.

Value	Name	Description
0	RR2000	2kHz
1	RR1000	1kHz
2	RR500	500Hz
3	RR250	250Hz
4	RR125	125Hz
5	RR62	62.5Hz

Bits 23:22 – DMFCS[1:0] Display Memory Update Frame Counter Selection

These bits select the frame counter to use to update display memory.

These bits are not synchronized.

Value	Name	Description
0	FC0	Frame Counter 0
1	FC1	Frame Counter 1
2	FC2	Frame Counter 2
3	NFC	Frame Counter event to DMU is forced to 0

Bits 21:20 – PRF[1:0] Power Refresh Frequency

These bits define the charge pump refresh frequency

These bits are not synchronized.

Value	Name	Description
0	PR2000	2kHz
1	PR1000	1kHz
2	PR500	500Hz
3	PR250	250Hz

Bit 19 – XVLCD External VLCD

This bit configures how VLCD is generated.

This bit is not synchronized.

Value	Description
0	Internal VLCD generation.
1	External VLCD generation.

Bits 17:16 – BIAS[1:0] Bias Setting

These bits configure the bias setting.

These bits are not synchronized.

Value	Name	Description
0	STATIC	Static
1	HALF	1/2 bias
2	THIRD	1/3 bias
3	FOURTH	1/4 bias

Bits 14:12 – CKDIV[2:0] Clock Divider

These bits configure the clock divider, refer to 42.6.1.5 LCD Frame Frequency.

Clock division value after prescaler DIV = CKDIV + 1.

These bits are not synchronized.

Bits 9:8 – PRESC[1:0] Clock Prescaler

These bits configure the clock prescaler, refer to 42.6.1.5 LCD Frame Frequency.

These bits are not synchronized.

Value	Name	Description
0	PRESC16	16
1	PRESC32	32
2	PRESC64	64
3	PRESC128	128

Bit 6 – RUNSTDBY Run in Standby

This bit controls the behavior of SLCD during standby sleep mode.

0: SLCD stops driving LCD panel.

1: SLCD continues to operate during standby sleep mode.

Bit 5 – WMOD Waveform Mode

This bit configures the waveform mode.

This bit is not synchronized.

Value	Name	Description
0	LP	Low Power Waveform Mode (type B, frame-inversion)
1	STD	Standard Waveform Mode (type A, bit-inversion).

Bits 4:2 – DUTY[2:0] Duty Ratio

These bits configure the duty ratio NB_COM for the LCD frame rate.

These bits are not synchronized.

Value	Name	Description
0x0	STATIC	NB_COM=1
0x1	HALF	NB_COM=2
0x2	THIRD	NB_COM=3
0x3	FOURTH	NB_COM=4
0x4	SIXTH	NB_COM=6
0x5	EIGHT	NB_COM=8

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

Value	Description
0	The peripheral is disabled.
1	The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the SLCD, except display/shadow memory to their initial state, and the SLCD will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded.

Due to synchronization, there is delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

Value	Description
0	There is no reset operation ongoing.
1	A reset operation is ongoing.

Name:	CTRLA
Offset:	0x00
Reset:	0x03D80000
Property:	PAC Write-Protection, Enable-Protected