42.8.6 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x0D |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRST | VLCDST | VLCDRT | FC2O | FC1O | FC0O | ||||
| Access | RW | RW | RW | RW | RW | RW | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – PRST Pump Run Status Toggle Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Pump Run Status Toggle Interrupt Disable/Enable bit, which disables the Pump Run Status Toggle interrupt.
| Value | Description |
|---|---|
| 0 | The Pump Run Status Toggle interrupt is disabled. |
| 1 | The Pump Run Status Toggle interrupt is enabled. |
Bit 4 – VLCDST VLCD Status Toggle Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding VLCD Status Toggle Interrupt Disable/Enable bit, which disables the VLCD Status Toggle interrupt.
| Value | Description |
|---|---|
| 0 | The VLCD Status Toggle interrupt is disabled. |
| 1 | The VLCD Status Toggle interrupt is enabled. |
Bit 3 – VLCDRT VLCD Ready Toggle Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding VLCD Ready Toggle Interrupt Disable/Enable bit, which disables the VLCD Ready Toggle interrupt.
| Value | Description |
|---|---|
| 0 | The VLCD Ready Toggle interrupt is disabled. |
| 1 | The VLCD Ready Toggle interrupt is enabled. |
Bit 2 – FC2O Frame Counter 2 Overflow Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Frame Counter 2 Overflow Interrupt Disable/Enable bit, which disables the Frame Counter 2 Overflow interrupt.
| Value | Description |
|---|---|
| 0 | The Frame Counter 2 Overflow interrupt is disabled. |
| 1 | The Frame Counter 2 Overflow interrupt is enabled. |
Bit 1 – FC1O Frame Counter 1 Overflow Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Frame Counter 1 Overflow Interrupt Disable/Enable bit, which disables the Frame Counter 1 Overflow interrupt.
| Value | Description |
|---|---|
| 0 | The Frame Counter 1 Overflow interrupt is disabled. |
| 1 | The Frame Counter 1 Overflow interrupt is enabled. |
Bit 0 – FC0O Frame Counter 0 Overflow Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Frame Counter 0 Overflow Interrupt Disable/Enable bit, which disables the Frame Counter 0 Overflow interrupt.
| Value | Description |
|---|---|
| 0 | The Frame Counter 0 Overflow interrupt is disabled. |
| 1 | The Frame Counter 0 Overflow interrupt is enabled. |