42.8.4 Control D
| Name: | CTRLD |
| Offset: | 0x08 |
| Reset: | 0x80 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DISPEN | FC2EN | FC1EN | FC0EN | CSREN | BLINK | BLANK | |||
| Access | RW | RW | RW | RW | RW | RW | RW | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DISPEN Display enable
These bit enable COM/SEG signal output.
These bits are not synchronized.
Bit 6 – FC2EN Frame Counter 2 Enable
This bit enables the frame counter 2.
| Value | Description |
|---|---|
| 0 | Frame counter 2 is disabled. |
| 1 | Frame counter 2 is enabled. |
Bit 5 – FC1EN Frame Counter 1 Enable
This bit enables the frame counter 1.
| Value | Description |
|---|---|
| 0 | Frame counter 1 is disabled. |
| 1 | Frame counter 1 is enabled. |
Bit 4 – FC0EN Frame Counter 0 Enable
This bit enables the frame counter 0.
| Value | Description |
|---|---|
| 0 | Frame counter 0 is disabled. |
| 1 | Frame counter 0 is enabled. |
Bit 2 – CSREN Circular Shift Register Enable
This bit enables the circular shift register.
| Value | Description |
|---|---|
| 0 | Circular shift register is disabled. |
| 1 | Circular shift register is ensabled. |
Bit 1 – BLINK Blinking Enable
This bit enables the blink mode.
| Value | Description |
|---|---|
| 0 | Blink mode is disabled. |
| 1 | Blink mode is ensabled. |
Bit 0 – BLANK Blank LCD
This bit allows user to blank all LCD segments (transparent).
| Value | Description |
|---|---|
| 0 | The state of the LCD segments is defined by shadow display memory. |
| 1 | Blank all LCD segments. |