42.8.2 Control B
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LREN | LRD[3:0] | ||||||||
| Access | RW | RW | RW | RW | RW | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BBEN | BBD[3:0] | ||||||||
| Access | RW | RW | RW | RW | RW | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 15 – LREN Low Resistance Enable
This bit enables/disables the low resistance network.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | Low resistance network is disabled. |
| 1 | Low resistance network is enabled. |
Bits 11:8 – LRD[3:0] Low Resistance Enable Duration
These bits configure the enable duration of the low resistance network.
Enable duration = (LRD + 1) x period of CLK_SLCD_OSC.
These bits are not synchronized.
Bit 7 – BBEN Bias Buffer Enable
This bit enables/disables the bias buffer.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | Bias buffer is disabled. |
| 1 | Bias buffer is enabled. |
Bits 3:0 – BBD[3:0] Bias Buffer Enable Duration
These bits configure the enable duration of the bias buffer.
Enable duration = (BBD + 1) x period of CLK_SLCD_OSC.
These bits are not synchronized.