46.13.6 Digital Phase Lock Loop (DPLL) Characteristics

Table 46-56. Fractional Digital Phase Lock Loop Characteristics⁽²⁾
Symbol	Parameter		Min.	Typ.	Max.	Unit
FIN	Input Clock Frequency		32	-	2000	kHz
FOUT	Output Clock Frequency	PL2	32	-	96	MHz
FOUT	Output Clock Frequency	PL0	32	-	48	MHz
Jp	Period jitter	PL0, Fin = 32 kHz, Fout = 32 MHz	-	3	6	%
		PL2, Fin = 32 kHz, Fout = 32 MHz		2	5
		PL0, Fin = 32 kHz, Fout = 48 MHz	-	3	4
		PL2, Fin = 32 kHz, Fout = 48 MHz		2	6
		PL2, Fin = 32 kHz, Fout = 96 MHz	-	3	4
		PL0, Fin = 32 kHz, Fout = 32 MHz	-	3	5
		PL2, Fin = 32 kHz, Fout = 32 MHz		3	6
		PL0, Fin = 2 MHz, Fout = 48 MHz	-	5	7
		PL2, Fin = 2 MHz, Fout = 48 MHz		3	6
		PL2, Fin = 2 MHz, Fout = 96 MHz	-	4	10
tLOCK	Lock Time	After startup, time to get lock signal Fin = 32 kHz, Fout = 96 MHz	-	1.1	1.5	ms
tLOCK	Lock Time	After startup, time to get lock signal Fin = 2 MHz, Fout = 96 MHz	-	24	35	µs
Duty	Duty cycle⁽¹⁾		40	50	60	%

Note:

These values are based on simulation. They are not covered by production test limits or characterization.
These characteristics are applicable only in LDO regulator mode and with a XOSC or XOSC32K reference.

Table 46-57. Power Consumption⁽¹⁾⁽²⁾
Symbol	Parameter	Conditions	TA	Min.	Typ.	Max.	Units
I_DD	Current Consumption	Fout = 48 MHz (PL0) - VDD=3.3V	Max. 85°C Typ. 25°C	-	339	432	µA
I_DD	Current Consumption	Fout = 96 MHz (PL2) - VDD=3.3V	Max. 85°C Typ. 25°C	-	678	777	µA

Note:

These characteristics are only applicable in LDO regulator mode.
These values are based on characterization. They are not covered in test limits in production.

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