46.13.5 Digital Frequency Locked Loop (DFLLULP) Characteristics

Table 46-53. Digital Frequency Locked Loop Characteristics (LDO Regulator)
Symbol	Parameter		Min.	Typ.	Max.	Unit
FIN	Input Clock Frequency		32	-	33	kHz
FOUT	Output Clock Frequency	PL2	-	-	32	MHz
FOUT	Output Clock Frequency	PL0	-	-	8	MHz
FOUT drift	Output Clock Frequency drift⁽²⁾	PL0, Fin = 32768 Hz 50 ppm Fout = 8 MHz	-3.8	-	3.2	%
FOUT drift	Output Clock Frequency drift⁽²⁾	PL2, Fin = 32768 Hz 50 ppm Fout = 32 MHz	-3.2	-	3.4	%
Jp	Period jitter (cycle to cycle jitter)⁽²⁾	PL0, Fin= 32 kHz 50 ppm, Fout = 8 MHz	-4	-	4	%
Jp	Period jitter (cycle to cycle jitter)⁽²⁾	PL2, Fin= 32 kHz 50 ppm, Fout = 32 MHz	-4.3	-	4.3	%
tLOCK	Lock Time	After startup, time to get lock signal Fin = 32768 Hz, Fout = 8MHz, PL0 Binary Search mode enabled	-	362	-	µs
tLOCK	Lock Time	After startup, time to get lock signal Fin = 32768 Hz, Fout = 32 MHz, PL2 Binary Search mode enabled	-	362	-	µs
Duty	Duty cycle⁽¹⁾		40	50	60	%

Note:

These values are based on simulation, and are not covered by test or characterization.
Core running on OSC16M, no peripheral activity.

Table 46-54. Digital Frequency Locked Loop Characteristics (Buck Regulator)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
FIN	Input Clock Frequency		32		33	kHz
FOUT	Output Clock Frequency	PL0	-	-	4.88	MHz
FOUT	Output Clock Frequency	PL2	-	-	26.78	MHz
FOUT drift	Output Clock Frequency drift⁽²⁾	PL0, FIN = 32 kHz, FOUT = 4.88 MHz	-16.3		38.9	%
FOUT drift	Output Clock Frequency drift⁽²⁾	PL2, FIN = 32 kHz, FOUT = 26.78 MHz	-8.7		16.3	%
Jp	Period Jitter⁽²⁾⁽³⁾ (cycle to cycle jitter)	PL0, FIN = 32 kHz, FOUT = 4.88 MHz	-7.8	-	8.1	%
Jp	Period Jitter⁽²⁾⁽³⁾ (cycle to cycle jitter)	PL2, FIN = 32 kHz, FOUT = 26.78 MHz	-5.0	-	4.6	%
tLOCK	Lock Time	After startup, time to get lock signal FIN = 32 kHz, FOUT = 4.88 MHz, PL0 Binary Search mode enabled	-	362	-	µs
tLOCK	Lock Time	After startup, time to get lock signal FIN = 32 kHz, FOUT = 26.78 MHz, PL2 Binary Search mode enabled	-	362	-	µs
Duty	Duty Cycle ⁽¹⁾		40	50	60	%

Note:

These values are based on simulation, and are not covered by test or characterization.
Asynchronous peripherals and accurate ADC measurement must not use DFLLULP with Buck Converter, alternatively use a clock configuration and source providing required accuracy. Synchronous-based peripherals must also consider frequency drift to ensure proper inter-device communications.
Core running on OSC16M, no peripheral activity.

Table 46-55. Power Consumption^{(1)
(2)}
Symbol	Parameters	Conditions	Ta	Min.	Typ.	Max.	Units
IDD	Current Consumption	Fout = 8 MHz (PL0) - VCC = 3.3V	Max 85°C Typ 25°C	-	33	93	µA
IDD	Current Consumption	Fout = 32 MHz (PL2) - VCC = 3.3V	Max 85°C Typ 25°C	-	144	223	µA

Note:

These characteristics are only applicable in LDO regulator mode.
These values are based on characterization, and are not covered in test limits in production.

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