33.7.8 Channel n Control
Important: For SAM
L11 Non-Secure accesses, read and
write accesses (RW*) are allowed only if the security attribution for the corresponding
channel (CHANNELx) is set as Non-Secured in the NONSECCHAN register.
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.
| Name: | CHANNEL |
| Offset: | 0x20 + n*0x08 [n=0..7] |
| Reset: | 0x00008000 |
| Property: | PAC Write-Protection, Mix-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ONDEMAND | RUNSTDBY | EDGSEL[1:0] | PATH[1:0] | ||||||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN[5:0] | |||||||||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – ONDEMAND Generic Clock On Demand
| Value | Description |
|---|---|
| 0 | Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled. |
| 1 | Generic clock is requested on demand while an event is handled |
Bit 14 – RUNSTDBY Run in Standby
This bit is used to define the behavior during standby sleep mode.
| Value | Description |
|---|---|
| 0 | The channel is disabled in standby sleep mode. |
| 1 | The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND bit. |
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
| Value | Name | Description |
|---|---|---|
| 0x0 | NO_EVT_OUTPUT | No event output when using the resynchronized or synchronous path |
| 0x1 | RISING_EDGE | Event detection only on the rising edge of the signal from the event generator |
| 0x2 | FALLING_EDGE | Event detection only on the falling edge of the signal from the event generator |
| 0x3 | BOTH_EDGES | Event detection on rising and falling edges of the signal from the event generator |
Bits 9:8 – PATH[1:0] Path Selection
These bits are used to choose which path will be used by the selected channel.
Note: The path choice can be limited by
the channel source, see the table in USERm.
Important: Only EVSYS channel 0 to 3 can be configured as synchronous or
resynchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | SYNCHRONOUS | Synchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| 0x2 | ASYNCHRONOUS | Asynchronous path |
| Other | - | Reserved |
Bits 5:0 – EVGEN[5:0] Event Generator Selection
These bits are used to choose the event generator to connect to the selected channel.
| Value | Event Generator | Description |
|---|---|---|
| 0x00 | NONE | No event generator selected |
| 0x01 | CLKFAIL | XOSC clock failure detection (OSCCTRL) |
| 0x02 | CLKFAIL | XOSC32K clock failure detection (OSC32KCTRL) |
| 0x03 | BOD33DET | SUPC BOD33 detection |
| 0x04-0x0B | PER0-7 | RTC period |
| 0x0C | ALARM0 | RTC alarm |
| 0x0C-0x0D | CMP0-1 | RTC comparison |
| 0x0E | TAMPER | RTC tamper detection |
| 0x0F | OVF | RTC overflow |
| 0x10 | PERD | RTC periodic interval daily |
| 0x11-0x18 | EXTINT0-7 | EIC external interrupt |
| 0x19-0x1C | CH0-3 | DMAC channel |
| 0x1D | OVF | TC0 overflow |
| 0x1E-0x1F | MCX0-1 | TC0 match/compare |
| 0x20 | OVF | TC1 overflow |
| 0x21-0x22 | MCX0-1 | TC1 match/compare |
| 0x23 | OVF | TC2 overflow |
| 0x24-0x25 | MCX0-1 | TC2 match/compare |
| 0x26 | RESRDY | ADC resolution ready |
| 0x27 | WINMON | ADC window monitor |
| 0x28-0x29 | COMP0-1 | AC comparator |
| 0x2A | WIN0 | AC window |
| 0x2B | EMPTY | DAC empty |
| 0x2C | EOC | PTC end of conversion |
| 0x2D | WCOMP | PTC window comparator |
| 0x2E | DATARDY | TRNG Data Ready |
| 0x2F-0x30 | LUT0-1 | CCL LUT output |
| 0x31 | ERR | PAC access error |