33.7.18 Channel Security Attribution Check
Important: This
register is only available for SAM
L11
and has no effect for SAM
L10.
Name: | NSCHKCHAN |
Offset: | 0x1DC |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CHANNEL7 | CHANNEL6 | CHANNEL5 | CHANNEL4 | CHANNEL3 | CHANNEL2 | CHANNEL1 | CHANNEL0 | ||
Access | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – CHANNELn Channel n Selection [n=0..7]
These bits selects the individual channels for security attribution check. If any channel selected in NSCHKCHAN has the corresponding bit in NONSECCHAN set to the opposite value, then the NSCHK interrupt flag will be set.
Value | Description |
---|---|
0 | 0-to-1 transition will be detected on corresponding NONSECCHAN bit. |
1 | 1-to-0 transition will be detected on corresponding NONSECCHAN bit. |