25.15.9 CWGxSTR
CWG Steering Control Register (1)
Note:
- The bits in this register apply only when MODE =
‘00x’(see CWGxCON025.15.5 CWGxCON0 and the “Steering Modes” section). - This bit is double-buffered when MODE =
‘001’.
| Name: | CWGxSTR |
| Address: | 0x614,0x61E,0x694 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRD | OVRC | OVRB | OVRA | STRD | STRC | STRB | STRA | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 4, 5, 6, 7 – OVRy Steering Data OVR'y' bit
| Value | Name | Description |
|---|---|---|
x |
STRy =
1 |
CWGx'y' output has the CWG data input waveform with polarity control from the POLy bit |
1 |
STRy = 0 and POLy =
x |
CWGx'y' output is high |
0 |
STRy = 0 and POLy =
x |
CWGx'y' output is low |
Bits 0, 1, 2, 3 – STRy STR'y' Steering Enable bit(2)
| Value | Description |
|---|---|
1 |
CWGx'y' output has the CWG data input waveform with polarity control from the POLy bit |
0 |
CWGx'y' output is assigned to value of the OVRy bit |