11.13.32 PIR9
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
- U3IF is a read-only bit. To clear the interrupt condition, all bits in the U3UIR register must be cleared
- U3EIF is a read-only bit. To clear the interrupt condition, all bits in the U3ERR register must be cleared.
- U3TXIF and U3RXIF are read-only bits and cannot be set/cleared by software.
| Name: | PIR9 |
| Offset: | 0x4B7 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWM4IF | PWM4PIF | CLC4IF | U3IF | U3EIF | U3TXIF | U3RXIF | |||
| Access | R | R/W | R/W/HS | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – PWM4IF PWM4 Parameter Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 6 – PWM4PIF PWM4 Period Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 5 – CLC4IF CLC4 Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 3 – U3IF UART3 Interrupt Flag(2)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 2 – U3EIF UART3 Framing Error Interrupt Flag(3)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 1 – U3TXIF UART3 Transmit Interrupt Flag(4)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 0 – U3RXIF UART3 Receive Interrupt Flag(4)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |