11.13.25 PIR2
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
| Name: | PIR2 |
| Offset: | 0x4B0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMA1AIF | DMA1ORIF | DMA1DCNTIF | DMA1SCNTIF | ADCH4IF | ADCH3IF | ADCH2IF | ADCH1IF | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DMA1AIF DMA1 Abort Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 6 – DMA1ORIF DMA1 Overrun Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 5 – DMA1DCNTIF DMA1 Destination Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 4 – DMA1SCNTIF DMA1 Source Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 3 – ADCH4IF ADC Context 4 Threshold Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 2 – ADCH3IF ADC Context 3 Threshold Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 1 – ADCH2IF ADC Context 2 Threshold Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 0 – ADCH1IF ADC Context 1 Threshold Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |