11.13.30 PIR7

Peripheral Interrupt Request Register 7
Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. PWM3IF is a read-only bit. To clear the interrupt condition, all bits in the PWM3GIR register must be cleared.
  3. I2C1EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C1ERR register must be cleared.
  4. I2C1IF is a read-only bit. To clear the interrupt condition, all bits in the I2C1PIR register must be cleared.
  5. I2C1TXIF and I2C1RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C1STAT1 must be set.
Name: PIR7
Offset: 0x4B5

Bit 76543210 
 PWM3IFPWM3PIFCLC3IF I2C1EIFI2C1IFI2C1TXIFI2C1RXIF 
Access RR/W/HSR/W/HSRRRR 
Reset 0000000 

Bit 7 – PWM3IF  PWM3 Parameter Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 6 – PWM3PIF PWM3 Period Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – CLC3IF CLC3 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – I2C1EIF  I2C1 Error Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – I2C1IF  I2C1 Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – I2C1TXIF  I2C1 Transmit Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – I2C1RXIF  I2C1 Receive Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PWM3IF is a read-only bit. To clear the interrupt condition, all bits in the PWM3GIR register must be cleared. I2C1EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C1ERR register must be cleared. I2C1IF is a read-only bit. To clear the interrupt condition, all bits in the I2C1PIR register must be cleared. I2C1TXIF and I2C1RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C1STAT1 must be set.