11.13.24 PIR1
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
- The external interrupt GPIO pin is selected by the INTxPPS register.
Name: | PIR1 |
Offset: | 0x4AF |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SMT1PWAIF | SMT1PRAIF | SMT1IF | CM1IF | ACTIF | ADIF | ZCDIF | INT0IF | ||
Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SMT1PWAIF SMT1 Pulse-Width Acquisition Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 6 – SMT1PRAIF SMT1 Period Acquisition Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 5 – SMT1IF SMT1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 4 – CM1IF CMP1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 3 – ACTIF Active Clock Tuning Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 2 – ADIF ADC Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 1 – ZCDIF ZCD Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 0 – INT0IF External Interrupt 0 Interrupt Flag(2)
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |