11.13.28 PIR5

Peripheral Interrupt Request Register 5

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PWM2IF is a read-only bit. To clear the interrupt condition, all bits in the PWM2GIR register must be cleared.
SPI2IF is a read-only bit. To clear the interrupt condition, all bits in the SPI2INTF register must be cleared.
SPI2TXIF and SPI2RXIF are read-only bits and cannot be set/cleared by software.

Name:	PIR5
Offset:	0x4B3


Bit	7	6	5	4	3	2	1	0
	PWM2IF	PWM2PIF	TMR3GIF	TMR3IF	TU16BIF	SPI2IF	SPI2TXIF	SPI2RXIF
Access	R	R/W/HS	R/W/HS	R/W/HS	R/W	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – PWM2IF PWM2 Parameter Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 6 – PWM2PIF PWM2 Period Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – TMR3GIF TMR3 Gate Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – TMR3IF TMR3 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – TU16BIF 16-bit Universal Timer B Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 2 – SPI2IF SPI2 Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – SPI2TXIF SPI2 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – SPI2RXIF SPI2 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PWM2IF is a read-only bit. To clear the interrupt condition, all bits in the PWM2GIR register must be cleared. SPI2IF is a read-only bit. To clear the interrupt condition, all bits in the SPI2INTF register must be cleared. SPI2TXIF and SPI2RXIF are read-only bits and cannot be set/cleared by software.