11.13.38 PIR15
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
| Name: | PIR15 |
| Offset: | 0x4BD |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMA8AIF | DMA8ORIF | DMA8DCNTIF | DMA8SCNTIF | TMR6IF | CRCIF | CLC8IF | NVMIF | ||
| Access | R/W | R/W | R/W | R/W | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DMA8AIF DMA8 Abort Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 6 – DMA8ORIF DMA8 Overrun Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 5 – DMA8DCNTIF DMA8 Destination Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 4 – DMA8SCNTIF DMA8 Source Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 3 – TMR6IF TMR6 Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 2 – CRCIF CRC Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 1 – CLC8IF CLC8 Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 0 – NVMIF NVM Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |