11.13.41 IPR2
Name: | IPR2 |
Offset: | 0x364 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DMA1AIP | DMA1ORIP | DMA1DCNTIP | DMA1SCNTIP | ADCH4IP | ADCH3IP | ADCH2IP | ADCH1IP | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
Bit 7 – DMA1AIP DMA1 Abort Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |
Bit 6 – DMA1ORIP DMA1 Overrun Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |
Bit 5 – DMA1DCNTIP DMA1 Destination Count Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |
Bit 4 – DMA1SCNTIP DMA1 Source Count Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |
Bit 3 – ADCH4IP ADC Context 4 Threshold Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |
Bit 2 – ADCH3IP ADC Context 3 Threshold Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |
Bit 1 – ADCH2IP ADC Context 2 Threshold Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |
Bit 0 – ADCH1IP ADC Context 1 Threshold Interrupt Priority
Value | Description |
---|---|
1 | High Priority |
0 | Low Priority |