11.13.1 INTCON0
| Name: | INTCON0 |
| Offset: | 0x4D6 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GIE/GIEH | GIEL | IPEN | INT2EDG | INT1EDG | INT0EDG | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 1 | 1 | 1 |
Bit 7 – GIE/GIEH Global Interrupt Enable
| Value | Name | Description |
|---|---|---|
| 1 | IPEN = 0 |
Enables all masked interrupts |
| 0 | IPEN = 0 |
Disables all interrupts |
| 1 | IPEN = 1 |
Enables all unmasked high-priority interrupts: The bit also needs to be set for enabling low-priority interrupts |
| 0 | IPEN = 1 |
Disables all interrupts |
Bit 6 – GIEL Global Low-Priority Interrupt Enable
| Value | Name | Description |
|---|---|---|
| n | IPEN = 0 |
Reserved, read as ‘0’ |
| 1 | IPEN = 1 |
Enables all unmasked low-priority interrupts, GIEH also needs to be set for low-priority interrupts |
| 0 | IPEN = 1 |
Disables all low-priority interrupts |
Bit 5 – IPEN Interrupt Priority Enable
| Value | Description |
|---|---|
| 1 | Enable priority levels on interrupts |
| 0 | Disable priority levels on interrupts, all interrupts are treated as high-priority interrupts |
Bit 2 – INT2EDG External Interrupt 2 Edge Select
| Value | Description |
|---|---|
| 1 | Interrupt on rising edge of the INT2 pin |
| 0 | Interrupt on falling edge of the INT2 pin |
Bit 1 – INT1EDG External Interrupt 1 Edge Select
| Value | Description |
|---|---|
| 1 | Interrupt on rising edge of the INT1 pin |
| 0 | Interrupt on falling edge of the INT1 pin |
Bit 0 – INT0EDG External Interrupt 0 Edge Select
| Value | Description |
|---|---|
| 1 | Interrupt on rising edge of the INT0 pin |
| 0 | Interrupt on falling edge of the INT0 pin |