11.2.3.2.3 Case X Multiplexor

The following Verilog example infers a multiplexor using a don’t care case x statement. Microchip does not recommend using don’t care case x statements in VHDL. VHDL synthesis tools do not typically support the don’t care value as well as Verilog tools.

//8 bit 4:1 multiplexor with don't care X, 3:1 equivalent mux
module mux4 (a, b, c, sel, q);
input [7:0] a, b, c;
input [1:0] sel;
output [7:0] q;
reg [7:0] q;
always @ (sel or a or b or c)
casex (sel)
2'b00: q = a;
2'b01: q = b;
2'b1x: q = c;
default: q = c;
endcase
endmodule