21.3 SmartTime Components

SmartTime is composed of two main tools:
  • The SmartTime Constraints Editor enables to view and edit timing constraints in the design. Constraints are sorted by category (requirements and exceptions) and by constraint type.
  • The SmartTime Timing Analyzer enables to analyze the design. Use this tool to apply timing constraints to the design.
Navigate between the SmartTime Constraints Editor and SmartTime Timing Analyzer by selecting Tools > Constraints Editor > Scenario or Tools > Timing Analyzer > Maximum Delay Analysis or Minimum Delay Analysis.
Note: Use the Timing Analyzer icon þÿ or Constraints Editor icon þÿ to toggle between the Timing Constraints View and Timing Analysis View.
SmartTime enables the following capabilities:
  • Browse through your design’s various clock domains to examine the timing paths and identify those that violate your timing requirements
  • Add and modify timing requirements and exceptions
  • Set constraints on a specific pin or a specific set of paths
  • Cross-probe objects and paths with NetlistViewer, ChipPlanner and ChipEditor tools
  • Create customizable timing reports
  • Navigate directly to the paths responsible for violating your timing requirements